In automotive electronics and high power RF technologies for example, devices such as III-V Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and SiC based Junction Gate Field-Effect Transistors (JFET) devices have enabled high voltage, high current and low on-resistance operation thereby resulting in high power and high efficiency operation. HEMTs and JFETs are examples of field effect transistor devices. The wide-band gap of GaN based devices offer robust and reliable devices capable of high voltage-high temperature operation. GaN technology is increasing in popularity due to better RF performance (lower capacitance and higher breakdown voltage) in comparison to silicon based devices used for example in power factor correction circuits used in power supplies for computing and portable communication devices.
GaN based field effect transistor devices are typically fabricated on silicon (Si), silicon carbide (SiC), and sapphire substrates. GaN HEMTs or SiC JFETs are typically depletion mode devices, therefore a negative gate voltage (when compared to the source voltage) and gate-drain biasing is required to switch the device. Such devices are therefore known as normally on devices. In other words when in use and without applying a gate source voltage the devices are in the on-state.
As a result of being normally on the input supply voltage is not isolated. Therefore at high voltages (for example 200-600 Volts) required for automotive and power supply applications, the inability to isolate the input voltage may increases the risk of damaging lower power ancillary circuits and components connected to such a high voltage device. Therefore driving a GaN HEMT or JFET device is a challenge for a number of reasons. Most notably a negative voltage bias is required to switch such normally on devices.
One technique for creating a normally off switch for such high voltage normally on devices is to use a cascode arrangement. In such an arrangement a low voltage FET 14 is placed in the source of the high voltage FET 10 device as illustrated in FIG. 1. When the low voltage FET is turned off, a negative gate voltage is created in the normally on high voltage device, thus turning off the high voltage device.
As shown in FIG. 1 the low voltage FET is an NMOS device. The NMOS low voltage FET is placed at the source of a high voltage device, where the drain of the low voltage FET is connected to the source of the high voltage device. The gate of the high voltage device and the source of the low voltage FET are connected such that they are the source terminal of the cascode device.
When the high voltage FET device is turned off, the drain-source voltage VDS of the low voltage FET (shown as Vx in FIG. 1) is determined by Eqn. 1, given below. Vx is a function of the threshold voltage of the high voltage device and the capacitance. In Eqn. 1 the capacitance COSS(MOS) is equal to the sum of the gate-drain capacitance CGD and the drain source capacitance CDS of the low voltage FET device.
                    Vx        =                                                            C                                  DS                  ⁡                                      (                    GaN                    )                                                              ·                              V                d                                      -                                          (                                                      C                                          OSS                      ⁡                                              (                        MOS                        )                                                                              +                                      C                                          GS                      ⁡                                              (                        GaN                        )                                                                                            )                            ·                              V                                  th                  ⁡                                      (                    GaN                    )                                                                                                          C                              DS                ⁡                                  (                  GaN                  )                                                      +                          (                                                C                                      OSS                    ⁡                                          (                      MOS                      )                                                                      +                                  C                                      GS                    ⁡                                          (                      GaN                      )                                                                                  )                                                          Eqn        .                                  ⁢        1            
From Eqn. 1, Vx which is the drain source voltage VDS of the low voltage FET is dependent on the applied voltage rating Vd, which is limited by the maximum voltage rating of the high voltage FET device. Typically the maximum voltage rating of the high voltage FET device will be in the range of 60 to 100 Volts.
When the cascode device has been turned off, that is no gate voltage Vg is applied to the low voltage FET, the drain source voltage Vx will change dependant on the respective reverse leakage currents of the high and low voltage FETs. The drain source leakage current IDS(GaN) of the high voltage FET will increase the drain source voltage Vx of the cascode device, whereas the drain source leakage current of the low voltage FET IDS(nmos) will reduce the drain source voltage Vx of the cascode device. Therefore the drain source voltage Vx of the low voltage FET will remain constant, decrease or increase and these situations can be expressed dependent on the leakage currents ID(GaN), IDS(nmos), and the gate leakage current of the high voltage FET IG(GaN).Vx constant: IDS(nmos)−IG(GaN)=ID(GaN)  1Vx decrease: IDS(nmos)−IG(GaN)>ID(GaN)  2Vx increase: IDS(nmos)−IG(GaN)<ID(GaN)  3
In each of the cases 1 to 3 above, since the source of the high voltage FET is at a higher potential than the gate the value of IG(GaN) will be negative.
For case 1, above, each of the leakage currents balance such that Vx remains constant. For case 2, above, Vx decreases to approximately the threshold voltage Vt of the high voltage FET, at which point ID(GaN) will increase until the leakage currents balance and Vx stabilises.
For case 3, above, Vx increases to the avalanche voltage of the low voltage FET, at which point IDS(nmos) will increase until the leakage currents balance and Vx stabilises. This case can cause the low voltage FET to avalanche.
Typically GaN based devices currently have a higher leakage currents when compared to Si based devices with the difference in leakages increasing the greater the difference in voltage rating. This means that the level of gate leakage in the GaN device is critical in determining whether case 3 occurs and the low voltage MOSFET is forced into avalanche.
Where the high voltage FET incorporates a Schottky gate, the majority of the drain leakage current will exit the high voltage FET via the gate. As such, the drain source leakage current of the high voltage device IDS(GaN) will be low, since the leakage current exits via the gate, little current will exit via the source hence IDS(GaN) will be low (and IG(GaN) will be high) and the situation given at case 2 above will occur. However, due to stability issues such as high frequency oscillations resulting from the high switching rate of GaN devices it may be necessary to include a series gate resistor at the gate of the high voltage FET to reduce the gate leakage current. If the gate resistance was high (IG(GaN) becomes low), case 3 could occur with Vx increasing to the avalanche voltage of the low voltage device.
Insulated gate GaN devices are preferred over Schottky gate devices due to the significantly lower gate leakage (due to the presence of the electrical isolation provided between the gate terminal and the GaN material), which when in use may result in reduced energy loss in the application. However, the avalanche situation of case 3 is more likely to occur in insulated gate devices due to the low leakage combined with the low. drain leakage current of the low voltage FET.
In some circumstances operating the low voltage device under avalanche conditions will result in increased device operating temperatures and this may not be problematic, for example where the device is not continuously operated or where sufficient heat sinking/packaging are provided. However, it is desirable for long term device reliability not to operate under avalanche conditions because hot carrier injection into the gate oxide of the low voltage MOSFET can result in increased Rds(on), threshold voltage Vt, reduction or increased drain source leakage and eventual device failure. Furthermore, if the avalanche voltage of the low voltage FET is greater than the maximum gate voltage of the high voltage FET then the high voltage FET could be damaged and failure could occur.